1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) panel, and more particularly, to an LCD panel and a fabricating method thereof that is adapted for improved reliability of keeping a cell gap by preventing defects caused by expansion of liquid crystal materials.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device controls light transmittance by applying an electric field to a liquid crystal layer, thereby displaying a picture. To this end, the LCD device includes an LCD panel having liquid crystal cells arranged in a matrix shape and a drive circuit to drive the LCD panel. The LCD panel includes a thin film transistor (TFT) array substrate and a color filter array substrate arranged to face each other, a spacer arranged to keep a fixed cell gap between the two substrates, and a liquid crystal material filled in the cell gap.
Various types of structures for the LCD panel have been proposed within the past few years to solve a specific problem. Specially, a spacer in the LCD panel provide a specified cell gap between the TFT array substrate and the color filter array substrate. However, reliability of maintaining the cell gap is reduced as the liquid crystals in the gap expand when exposed to high temperatures. To solve such a problem, a dual spacer structure for the LCD panel has been proposed recently.
FIG. 1 is a plan view representing an LCD panel adopting a dual spacer structure of the related art. As shown in FIG. 1, the LCD panel is centered around a TFT array substrate and a column spacer. FIG. 2A is a cross sectional view illustrating the TFT array substrate taken along line I-I′ of FIG. 1, and FIG. 2B is a cross sectional view illustrating the TFT array substrate taken along line II-II′.
The LCD panel shown in FIGS. 1, 2A, and 2B includes a color filter array substrate 60, a TFT array substrate 70, and a liquid crystal material (not shown) injected into an inner space between the color filter array substrate 60 and the TFT array substrate 70. The color filter array substrate 60 includes a black matrix 64, a color filter 66, a main column spacer 24, an auxiliary column spacer 23, and an upper alignment film 58 formed on an upper substrate 62. The TFT array substrate 70 includes a thin film transistor 6, a pixel electrode 18, and a lower alignment film 52 formed on a lower substrate 42.
In the color filter array substrate 60, the black matrix 64 is formed on the upper substrate 62 in areas corresponding to gate lines 2, data lines 4, and TFTs 6 formed on the lower substrate 42, and provides a cell area where the color filter 66 is to be formed. The black matrix 64 prevents light leakage and absorbs external light, thereby increasing contrast. A common electrode (not shown) can be formed on the color filter 66 in a TN (twisted nematic) mode, which uses a vertical direction electric field. In contrast, a common electrode (not shown) can be formed on the TFT array substrate 70 in an IPS (in-plane switch) mode, which uses a horizontal direction electric field.
The TFT array substrate 70 includes a gate line 2 and a data line 4 formed on the lower substrate 42 to cross each other with a gate insulating film 44 therebetween, a TFT 6 formed at each crossing part, and a pixel electrode 18 formed in a cell area defined by the crossing structure. The TFT array substrate 70 also includes a storage capacitor formed in an overlap portion of the gate line 2 and a next-stage pixel electrode 18. (FIG. 1 shows a storage capacitor 20 of the next pixel area.)
The TFT 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 18, and an active layer 14 formed over the gate electrode 8 with a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is overlapped with the data line 4 and the source and drain electrodes 10, 12, and includes a channel part between the source electrode 10 and the drain electrode 12. An ohmic contact layer 47 is further formed on the active layer 14 for being in ohmic contact with the data line 4 and the source and drain electrodes 10, 12. The active layer 114 and the ohmic contact layer 147 defines a semiconductor pattern 48.
In the TFT 6, a pixel voltage signal supplied to the data line 4 charges the pixel electrode 18 in response to a gate signal supplied to the gate line 2. To this end, the pixel electrode 18 is connected to the drain electrode 12 of the TFT 6 through a contact hole 17 that penetrates a passivation film 50. The pixel electrode 18 generates a potential difference with the common electrode (not shown). The potential difference causes liquid crystals, which are located between the TFT array substrate 70 and the color filter array substrate 60, to rotate by dielectric anisotropy. The rotation of the liquid crystals transmits light, which is incident through the pixel electrode 18 from a light source (not shown), to the upper substrate.
The storage capacitor 20 shown in FIG. 1 is actually a storage capacitor for the next stage pixel. Hence, the storage capacitor 20 includes a pre-stage gate line 2 and a pixel electrode 18 (partially shown) that overlaps the pre-stage gate line 2 with the gate insulating film 44 and the passivation film 50 formed therebetween. The storage capacitor 20 helps the pixel voltage, which is charged in the pixel electrode 18, to be kept until the next pixel voltage is charged.
The main column spacer 24 is located in an area overlapping the storage capacitor 20, and the auxiliary column spacer 23 is located in an area overlapping the gate line 2. Further, the main column spacer 24 and the auxiliary column spacer 23 are located to overlap the black matrix 64 of the color filter array substrate 60.
The main column spacer 24 is in contact with the TFT array substrate 70 to maintain a cell gap. To this end, the storage capacitor 20 located in a lower part of the main column spacer 24 and is defined by a stepped difference formed by an upper storage electrode 54 made of the source/drain pattern and the semiconductor pattern.
The auxiliary column spacer 23 is arranged to float above the TFT array substrate 70 at ordinary times and acts to prevent a defect that is generated when liquid crystals expand. Additionally, when an external pressure is applied to the substrates, the auxiliary column spacer 23 comes in contact with the TFT array substrate 70, thereby reinforcing the main column spacer 24 to maintain the cell gap.
In the LCD panel having the dual spacer structure of the related art, if the passivation film 50 of the TFT array substrate 70 is formed of an organic material such as photo-acryl, the dual spacer structure does not perform its function properly. For instance, the LCD panel shown in FIG. 3 has the passivation film 50 of the TFT array substrate 70 formed of an organic material. When the passivation film 50 is formed with an organic material, no stepped difference is generated within the TFT array substrate 70. Hence, there is no height difference between the main column spacer 24 and the auxiliary column spacer 23. As a result, in the LCD panel adopting the organic passivation film 50 of the related art, the advantages of preventing a defect from liquid crystal expansion and increased reliability of the cell obtained from using the dual spacer structure are lost.